1. Field of the Invention
The present invention relates to dual port memories including random access memories allowing random access and sequential access memories allowing sequential access, and particularly to an improvement in data transfer in dual port memories.
2. Description of the Related Art
Image information is digitally processed in work stations, personal computers and others. Frame buffer memories called video RAMs (Random Access Memories) are used for displaying such image information on displays. In this case, one row in the video RAM corresponds to one horizontal scanning line in a screen of the display. The frame buffer memory stores the image data of one frame.
Conventional RAMs cannot simultaneously write and read the data. Therefore, if the conventional RAM is used as the video RAM, a CPU (central processing unit) cannot access the video RAM while pixel data is being displayed. The CPU accesses the video RAM only during horizontal retracing. This reduces a data processing rate of the system.
For the above reason, multiport RAMs which allow simultaneous and asynchronous output of the pixel data to the displays and the access by the CPUs have been generally and widely used as memories for image processing.
FIG. 10 schematically shows a construction of a graphic processing system using a multiport memory (multiport RAM).
The system in FIG. 10 employs a typical example of the multiport memory, i.e., a dual port memory 900 which has one randomly accessible RAM port and one serially accessible SAM port. Dual port memory 900 is used as a video RAM for a frame buffer. Dual port memory 900 includes a dynamic random access memory array (will be called as "memory array") 901 which can be accessed in a random sequence and a serial register 902 which can be accessed only in a serial manner.
Generally, a portion including memory array 901 is called as a RAM port, and a portion including serial register 902 is called as a SAM port. Serial register 902 can store data for one row in memory array 901.
CPU 910 accesses dual port memory 900 in the random sequence for carrying out necessary processings. A display 930 displays pixel data supplied from serial register 902. A CRT display controller 920 generates a control signal for controlling an operation of dual port memory 900.
In dual port memory 900, the pixel data for one row is transferred from the RAM port to the SAM port in one transferring operation. While the pixel data for one row is being serially supplied to display 930, CPU 910 can randomly access the RAM port to carry out the necessary operation.
Therefore, if the transfer of data from the RAM port to the SAM port is carried out in the horizontal retracing period, CPU 910 can perform the following operations in a remaining horizontal scanning period. That is; CPU 910 can randomly read the data in memory array 901, also can appropriately process and write the data in memory array 901 again.
An operation timing of dual port memory 900 is controlled by CRT display controller 920. CRT display controller 920 inhibits the access by CPU 910 while the data is being transferred from the RAM port to the SAM port.
In this manner, if dual port memory 900 is used as the video RAM for the frame buffer, CPU 910 can access dual port memory 900 while performing the display on display 930. Therefore, the performance and operation rate of the system are remarkably improved.
FIG. 11 is a block diagram showing an example of a whole construction of the dual port memory. A dual port memory 1 is formed on a semiconductor chip.
In the dual port memory, input and output of data are generally performed by a multiple bit unit, such as 4 bit unit (.times.4 construction) or 8 bit unit (.times.8 construction). However, FIG. 11 shows a construction which performs inputting and outputting of the data by one bit unit.
In FIG. 11, dual port memory 1 includes a random access memory array (will be called as "memory array") 100 allowing random access and a serial register 300 allowing only serial access. Memory array 100 includes a plurality of dynamic memory cells which are arranged in a matrix form including a plurality of rows and a plurality of columns. Serial register 300 includes a plurality of static memory cells (registers) arranged in one row. Memory array 100 and portions related thereto is called as a RAM port 10. Serial register 300 and portions related thereto are called as a SAM port 30.
An address buffer circuit 400 receives external address signals A0-An supplied to an address input terminal 500, and generates an internal row address signal 400a and an internal column address signal 400b in a time sharing manner. A row decoder 101 is responsive to internal row address signal 400a supplied from address buffer circuit 400 to select a corresponding row in memory array 100. Column decoder 102 is responsive to internal column address signal 400b supplied from address buffer circuit 400 to generate a column selecting signal for selecting one corresponding column in memory array 100.
Sense amplifier circuit 105 senses and amplifies the data read from selected one row in memory array 100. An I/O gate 106 is responsive to column selecting signal supplied from column decoder 102 to transmit one bit in the data for one row amplified by sense amplifier circuit 105 to an I/O common bus 104.
RAM I/O buffer circuit 103 includes an input circuit and an output circuit. In a data reading operation, I/O buffer circuit 103 produces external read data from the data on I/O common bus 104, and transmits the same to an external data I/O terminal 504. In a data writing operation, I/O buffer circuit 103 produces internal write data from external write data supplied to external data I/O terminal 504, and transmits the same to I/O common bus 104.
Transfer circuit 200 transfers the data for one row between an arbitrary row in memory array 100 and serial register 300. A serial selector 302 sequentially selects memory cells in serial register 300. Data read from selected memory cell is supplied to an I/O common bus 304.
A SAM I/O buffer circuit 303 includes an input circuit and an output circuit. In the reading operation of data, I/O buffer circuit 303 produces external read data from the data on I/O common bus 304, and transmits the same to an external data I/O terminal 505. In the writing operation of data, I/O buffer circuit 303 produces internal write data from external write data supplied to external data I/O terminal 505, and transmits the same to I/O common bus 304.
Dual port memory 1 includes, as peripheral circuits, an internal clock generating circuit 401, an SC buffer and shift clock generating circuit 402, and an SE buffer circuit 403.
Internal clock generating circuit 401 receives control signals /RAS, /CAS, /WB; WE, /DT; /OE, which are externally applied from an external clock input terminal 501, to generate various internal control signals. SC buffer and shift clock generating circuit 402 includes a signal converting circuit like a counter, and receives a control signal /SE applied to a control signal input terminal 503 to generate an internal control signal for activating SAM I/O buffer circuit 303.
Control signal /RAS determines timing by which address buffer circuit 400 captures, as the internal row address signal, the external address signal applied to address input terminal 500, and also serves as a row address strobe signal for controlling an operation of row selecting system in RAM port 10. Control signal /CAS determines timing by which address buffer circuit 400 captures, as the internal column address signal, the external address signal applied to address input terminal 500, and also serves as a column address strobe signal for controlling an operation of a column selecting system in RAM port 10.
Control signals /WB and WE are control signals for designating a write per bit operation and a data writing operation. The write per bit operation is a mode in which writing related to a predetermined bit is inhibited when RAM port 10 performs input and output of the data by a multiple bit unit. Control signals /DT and /OE are control signals for designating a data transfer mode in which data is transferred between RAM port 10 and SAM port 20, and designating a data output mode.
Dual port memory 1 further includes an address pointer 410. Address pointer 410 is responsive to the control signal supplied from internal clock generating circuit 401 to latch the internal column address signal supplied from address buffer circuit 400 and apply the same to serial selector 302 as a start address signal 400c.
Then, an operation of dual port memory 1 in FIG. 11 will be described below. RAM port 10 is accessed similarly to the access in a conventional dynamic RAM.
Specifically, at a time of fall of control signal /RAS, external address signals A0-An being applied to address input terminal 500 are captured by address buffer circuit 400, and are applied to row decoder 101 as internal row address signals 400a. Row decoder 101 is responsive to an internal row address signal 400a to select one row in memory array 100, and sets a potential of corresponding row selection line (word line) at an active state of "H". Thereby, data is read from the memory cells in the selected one row. The data for one row is amplified and held by sense amplifier circuit 105.
When, control signal /CAS falls, address buffer circuit 400 captures external address signals A0-An applied to address input terminal 500, and applies the same, i.e., internal column address signals 400b to column decoder 102. Column decoder 102 decodes internal column address signal 400b, and generates the column selecting signal for selecting a corresponding column in memory array 100. Column selecting signal selects one bit in the data for one row held by sense amplifier circuit 105, and the selected data is read through I/O gate 106 to I/O common bus 104.
In the data reading operation, when control signals /DT and /OE are activated to be "L", the output circuit included in RAM I/O buffer circuit 103 is activated. Thereby, external read data is formed from the data on I/O common bus 104, and is supplied to data I/O terminal 504.
In the data writing operation, when control signals /WB and /WE are activated to be "L", the input circuit included in RAM I/O buffer circuit 103 is activated at the timing of fall of the control signal /CAS or the timing of fall of the control signals /WB and /WE which is later. Thereby, the data applied to data I/O terminal 504 is captured to form the internal write data signal, which is transmitted to I/O common bus 104.
Since a driving capability of the write data signal is higher than that of the read data signal, the read data amplified by sense amplifier circuit 105 is rewritten and replaced with the write data. In this manner, the data is written in one memory cell in memory array 100.
Then, a data transfer operation as well as data writing and reading operations of SAM port 30 will be described below.
SAM port 30 is selectively set to be in the data reading mode and the data writing mode, depending on a kind of the transfer cycle which was carried out before the setting of the mode. When memory array 100 transmits the data to serial register 300 through transfer circuit 200 (i.e., in the read transfer cycle), SAM port 30 is set in the data reading mode.. When serial register 300 transfers the data to memory array 100 through transfer circuit 200 (write transfer cycle), SAM port 30 is set in the data writing mode.
First, the operation in the data reading mode will be described below.
In the normal reading cycle in RAM port 10, when control signals /DT and /OE are set in the active state "L", control signals /WB and /WE are set in the inactive state "H", and control signal /SE is set in an arbitrary state at the time of activation of the control signal /RAS ("L"), the read transfer cycle starts. Thereby, after the data of the memory cells in one row in memory array 100 is sensed and amplified, transfer circuit 200 is activated in response to the rising of control signals /DT and /OE. Consequently, the data for one row is transferred to serial register 300.
Then, the internal column address signal, which was strobed when control signal /CAS falls, is loaded to address pointer 410. Internal column address signal is applied to serial selector 302 as start address signal 400c. Thereby, an initial selected bit position (selected address) in serial selector 302 is designated.
Thereafter, a signal conversion circuit included in SC buffer and shift clock generating circuit 402 increments the selected address in serial selector 302 one by one. Thereby, the data for one row stored in serial register 300 is sequentially supplied through the output circuit included in SAM I/O buffer circuit 303 to external data I/O terminal 505.
Then, the operation of SAM port 30 in the data writing mode will be described below.
First, at the time of activation ("L") of control signal /RAS, the write transfer cycle starts when control signals /WB and /WE are set in the active state "L", control signals /DT and /OE are set in the active state "L", and control signal /SE is set in the active state "L". Immediately after this, the data of serial register 300 is transferred through transfer circuit 200 to memory array 100.
At this time, row decoder 101 selects one row in memory array 100. Therefore, the data for one row transferred from serial register 300 may compete with the data read from the memory cells in one row selected in memory array 100.
However, an amount of charges supplied from serial register 300 is generally larger than an amount of charges supplied from memory array 100. Consequently, sense amplifier circuit 105 does not amplify the data read from the memory cells in the row selected in the memory array 10, but amplifies the data transferred from serial register 300. Consequently, the data transferred from serial register 300 is written in the memory cells in the row selected in memory array 100.
When control signal /CAS falls to "L", the internal column address signal strobed by address buffer circuit 400 is loaded in the address pointer 410. This internal column address signal is applied to serial selector 302 as start address signal 400c. Thereby, the initial selected bit (selected address) in serial selector 302 is designated.
Thereafter, SC buffer and shift clock generating circuit 402 increments the selected address in serial selector 302 one by one each time external clock signal SC changes. Consequently, the write data applied to external data I/O terminal 505 is sequentially applied to selected address in serial selector 302 through the input circuit included in SAM I/O buffer circuit 303.
As described above, writing of the data in serial register 300 and reading of the data from serial register 300 are carried out in response to external clock signal SC. In this case, it is not necessary to perform the row selecting operation and the column selecting operation, as is done in the conventional dynamic RAM, and thus SAM port 30 is accessed at a high speed in a range from 10 ns to 30 ns. Therefore, the dual port memories have been widely used in the image processing purposes in which a large amount of data must be processed.
In recent years, memory array portions in dynamic RAMs (will be called as "DRAMs") have increased to e.g., 1 Mbits, 4 Mbits and 16 Mbits, and thus the increase of the power consumption has often posed a problem.
FIG. 12 is a diagram for showing a dividing operation of the DRAM. The dividing operation of the DRAM is effective measures for solving the problem of increase of the power consumption.
FIG. 12 shows an example, in which a memory array 1100 having a storage capacity of 1 Mbits is divided into two blocks each having a half storage capacity. FIG. 12 shows an actual arrangement of memory array region AR in FIG. 11.
In FIG. 12, memory array 1100 is divided into two memory array blocks 1100a and 1100b. A serial register 3000 is disposed between two memory array blocks 1100a and 1100b. A sense amplifier circuit 1200a is arranged correspondingly to memory array block 1100a, and a sense amplifier circuit 1200b is arranged correspondingly to memory array block 1100b.
Memory array 1100 corresponds to memory array 100 shown in FIG. 11, and a serial register 3000 corresponds to a serial register 300 shown in FIG. 11. Sense amplifier circuits 1200a and 1200b each correspond to a sense amplifier circuit 105 shown in FIG. 11.
Memory array 1100 is divided such that memory array blocks 1100a and 1100b are disposed in a column direction. Thus, memory array block 1100a includes memory cells from 0th row to 255th row (X0-X255), and memory array block 1100b includes memory cells from 256th row to 511th row (X256-X511).
For example, when a row selection line (word line) 1010 is activated, the data is read from memory cells in one row connected to row selection line 1010, and the data for one row is amplified by sense amplifier circuit 1200a. In this case, sense amplifier circuit 1200a corresponding to memory array block 1100a operates, and sense amplifier circuit 1200b corresponding to memory array block 1100b does not operate. Thus, 1/2-divisional operation is carried out. This method has been employed in DRAMs of 1 Mbits and is well-known.
In this manner, the power consumption of the DRAMs are reduced.
Then, such a construction will be considered that a DRAM having a memory array in which a 1/4-division operation is to be carried out is applied to the dual port memory. FIGS. 13, 14 and 15 are block diagrams showing a construction which can be contemplated when the memory array effecting the 1/4-divisional operation is applied to the dual port memory.
First, in FIG. 13, memory array 1100 is divided into four memory array blocks 1100a, 1100b, 1100c and 1100d. Memory array block 1100a includes the memory cells from 0th row to 127th row. Memory array block 1100b includes the memory cells from 128th row to 255th row. Memory array block 1100c includes the memory cells from 256th row to 383th row. Memory array block 1100d includes the memory cells from 384th row to 511th row.
A serial register 1300a is disposed at a side of memory array block 1100a, and a serial register 1300b is disposed between memory array blocks 1100b and 1100c. A serial register 1300c is disposed at a side of memory array block 1100d. Further, a sense amplifier circuit 1200a is disposed between memory array blocks 1100a and 1100b, and a sense amplifier circuit 1200b is disposed between memory array blocks 1100c and 1100d.
Sense amplifier circuits 1200a and 1200b are formed of shared sense amplifier circuits, which are well known and disclosed, e.g., in the Japanese Patent Publication Nos. 61-46918 and 62-55234, in order to reduce occupied areas. Shared sense amplifier circuit 1200a operates for array blocks 1100a and 1100b, and shared sense amplifier circuits 1200b operates for memory array blocks 1100c and 1100d.
In an example in FIG. 13, the serial registers cannot be disposed at one position and are disposed at three positions.
In FIG. 14, serial register 1300a is disposed between memory array blocks 1100a and 1100b, and serial register 1300b is disposed between memory array blocks 1100c and 1100d. Also, sense amplifier circuit 1200a is disposed at a side of memory array block 1100a, and sense amplifier circuit 1200b is disposed between memory array blocks 1100b and 1100c. A sense amplifier circuit 1200c is disposed at a side of memory array block 1100d.
In an example in FIG. 14, the serial registers are disposed at two position. In FIG. 15, sense amplifier circuit 1200a and serial register 1300a are disposed between memory blocks 1100a and 1100b, and sense amplifier circuit 1200b and serial register 1300b are disposed between memory array blocks 1100c and 1100d.
Also in an example in FIG. 15, the serial registers are disposed at two positions. In the dual port memory in FIG. 12 which uses the memory array performing the 1/2-divisional operation, the data can be transferred from an arbitrary row in memory array 1100 to serial register 1300, as shown in FIG. 16, and the data can be transferred from serial register 1300 to an arbitrary row in memory array 1100.
However, the data transmitting method is restricted in the dual port memory having the memory array which performs the 1/4-divisional operation.
In the construction in FIG. 13, memory array block 1100a can transfer the data only to serial register 1300a, and cannot transfer the data to serial registers 1300b and 1300c, because memory array blocks 1100b, 1100c and 1100d are inactive while memory array block 1100a is operating, and only serial register 1300a is connected to operating memory array block 1100a.
For the same reason, memory array blocks 1100b and 1100c can transfer the data only to serial register 1300b, and memory array block 1100d can transfer the data only to serial register 1300c.
Conversely, serial register 1300a can transfer the data only to memory array block 1100a, and serial register 1300b can transfer the data only to memory array blocks 1100b and 1100c. Serial register 1300c can transfer the data only to memory array block 1100d. The data cannot be transferred in a manner other than those described above.
In the constructions shown in FIGS. 14 and 15, memory array blocks 1100a and 1100b can transfer the data only to serial register 1300a as shown in FIG. 18. Memory array blocks 1100c and 1100d can transfer the data only to serial register 1300b.
Conversely, serial register 1300a can transfer the data only to memory array blocks 1100a and 1100b, and serial register 1300b can transfer the data only to memory array blocks 1100C and 1100d.
As described above, the conventional dual port memory, which uses the memory array performing the 1/4-dividing operation, cannot transfer the data between the memory array block and the serial register which are disposed at physically separated positions. As described above, if the divisional operation such as 1/4-divisional operation and 1/8-divisional operation is applied to the memory array, the transfer of data between the RAM port and the SAM port is restricted. As the capacity of the DRAM increases to, e.g., 4 Mbits, 16 Mbits and 64 Mbits, the restriction on the data presents a more serious problem.
Further, in the conventional dual port memory 1 in FIG. 11, sense amplifier circuit 105 is required to charge and discharge an excessive load formed of the bit lines and others during the transfer of data from memory array 100 to serial register 300. Therefore, charging and discharging of such load cause an instable state of sense amplifier circuit 105, and a time is required for restoration thereof to a stable state. Also, noise applied to sense amplifier circuit 105 may serve as a trigger, which causes a malfunction such as inversion of the data.
In the conventional dual port memory 1 shown in FIG. 11, data cannot be externally written in serial register 300, while sense amplifier circuit 105 is amplifying the data transmitted from serial register 300 to memory array 100. This unpreferably increases the access time to serial register 300.